In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-N multiplying delay-locked loop,(MDLL) is presented. The fractional spur is less than -59.0 dBc, and the reference spur is -64.5 dBc. The power consumptions are 1.85 mW and 1.22 mW, corresponding to figures of merit,(FOM) of -240.4 dB and -245.5 dB.