ssc letter

A 0.4-ps-jitter− 52-dBc-spur synthesizable injection-locked PLL with self-clocked nonoverlap update and slope-balanced subsampling BBPD

In this letter, a fully synthesizable injection-locked phase-locked loop (IL-PLL) is presented.The PLL achieved a 0.4-ps integrated jitter at 1-GHz output frequency with −52-dBc reference spur. The power consumptions are 1.2 mW, corresponding to figures of merit of −247.2 dB.