fractional-N ADPLL

A Sub-mW Fractional- ADPLL With FOM of −246 dB for IoT Applications

This paper presents a sub-mW fractional-N all-digital phase-locked loop (ADPLL) with scalable power consumption, which achieves an figure of merit (FOM) of -246 dB.

A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique

This paper presents a fully-synthesizable fractional-N injection-locked PLL in 65 nm CMOS.The power consumption is 2.5 mW and 2.2 mW, corresponding to an FoM of -234.4 dB and -246.7 dB.

A 0.98 mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of− 246dB for IoT applications in 65nm CMOS

This paper presents a 2.0-to-2.8GHz 653μW fractional-N ADPLL that achieves -242dB FOM in 65nm CMOS for 2.4GHz ISM band applications.