all-digital IL-PLL

A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration

In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-N multiplying delay-locked loop,(MDLL) is presented. The fractional spur is less than -59.0 dBc, and the reference spur is -64.5 dBc. The power consumptions are 1.85 mW and 1.22 mW, corresponding to figures of merit,(FOM) of -240.4 dB and -245.5 dB.

A 0.4-ps-jitter− 52-dBc-spur synthesizable injection-locked PLL with self-clocked nonoverlap update and slope-balanced subsampling BBPD

In this letter, a fully synthesizable injection-locked phase-locked loop (IL-PLL) is presented.The PLL achieved a 0.4-ps integrated jitter at 1-GHz output frequency with −52-dBc reference spur. The power consumptions are 1.2 mW, corresponding to figures of merit of −247.2 dB.

A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique

This paper presents a fully-synthesizable fractional-N injection-locked PLL in 65 nm CMOS.The power consumption is 2.5 mW and 2.2 mW, corresponding to an FoM of -234.4 dB and -246.7 dB.

A 0.42 ps-jitter− 241.7 dB-FOM synthesizable injection-locked PLL with noise-isolation LDO

This paper presents a supply regulated synthesizable injection-locked PLL (IL-PLL), using a noise-isolation LDO.