Publications

Bangan Liu, Yuncheng Zhang, Junjun Qiu, Huy Cu Ngo, Wei Deng, Kengo Nakata, Toru Yoshioka, Jun Emmei, Jian Pang, Aravind Tharayil Narayanan, Haosheng Zhang, Teruki Someya, Atsushi Shirane, Kenichi Okada (2020). A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration. In TCAS-I.

Kenji Tanaka, Yuki Arikawa, Kenji Kawai, Junichi Kato, Tsuyoshi Ito, Huy Cu Ngo, Kazutaka Morita, Fumiaki Miura, Takeshi Sakamoto, Satoshi Shigematsu (2019). Distributed Deep Learning with FPGA Ring Allreduce. In ISC.

Kenji Tanaka, Yuki Arikawa, Kenji Kawai, Junichi Kato, Tsuyoshi Ito, Huy Cu Ngo, Kazutaka Morita, Takeshi Sakamoto, Satoshi Shigematsu (2018). Large-Message Size Allreduce at Wire Speed for Distributed Deep Learning. In SC.

Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada (2018). A Sub-mW Fractional- ADPLL With FOM of −246 dB for IoT Applications. In JSSC.

Bangan Liu, Huy Cu Ngo, Kengo Nakata, Wei Deng, Yuncheng Zhang, Junjun Qiu, Toru Yoshioka, Jun Emmei, Haosheng Zhang, Jian Pang, Aravind Tharayil Narayanan, Dongsheng Yang, Hanli Liu, Kenichi Okada, Akira Matsuzawa (2018). A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. In CICC.

Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada, Akira Matsuzawa (2018). A 0.98 mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of− 246dB for IoT applications in 65nm CMOS. In ISSCC.

Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima, Kenichi Okada, Akira Matsuzawa (2017). A 0.42 ps-jitter− 241.7 dB-FOM synthesizable injection-locked PLL with noise-isolation LDO. In ISSCC.