Huy Cu Ngo

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A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration
Distributed Deep Learning with FPGA Ring Allreduce
A 0.4-ps-jitter− 52-dBc-spur synthesizable injection-locked PLL with self-clocked nonoverlap update and slope-balanced subsampling BBPD
Large-Message Size Allreduce at Wire Speed for Distributed Deep Learning
A Sub-mW Fractional- ADPLL With FOM of −246 dB for IoT Applications
A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique
A 0.98 mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of− 246dB for IoT applications in 65nm CMOS
A 0.42 ps-jitter− 241.7 dB-FOM synthesizable injection-locked PLL with noise-isolation LDO